View LTC2657BCUFD-H16PBF_8928998.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc2657 1 2657f block diagram description octal i 2 c 16-/12-bit rail-to-rail dacs with 10ppm/c max reference the ltc ? 2657 is a family of octal i 2 c 16-/12-bit rail-to- rail dacs with integrated 10ppm/c max reference. the dacs have built-in high performance, rail-to-rail, output buffers and are guaranteed monotonic. the ltc2657-l has a full-scale output of 2.5v with the integrated reference and operates from a single 2.7v to 5.5v supply. the ltc2657-h has a full-scale output of 4.096v with the integrated reference and operates from a 4.5v to 5.5v supply. each dac can also operate with an external reference, which sets the full-scale output to 2 times the external reference voltage. the parts use a 2-wire i 2 c compatible serial interface. the ltc2657 operates in both the standard mode (maximum clock rate of 100khz) and the fast mode (maximum clock rate of 400khz). the ltc2657 incorporates a power-on reset circuit that is controlled by the porsel pin. if porsel is tied to gnd the dacs reset to zero-scale at power-up. if porsel is tied to v cc , the dacs reset to mid-scale at power-up. l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5396245, 6891433 and patent pending. features applications n integrated reference 10ppm/c max n maximum inl error: 4lsb n guaranteed monotonic over temperature n selectable internal or external reference n 2.7v to 5.5v supply range (ltc2657-l) n integrated reference buffers n ultralow crosstalk between dacs(0.8nv?s) n power-on-reset to zero-scale/mid-scale n 400khz i 2 c interface n tiny 20-lead 4mm 5mm qfn and 20-lead thermally enhanced tssop packages n mobile communications n process control and industrial automation n instrumentation n automatic test equipment n automotive register register internal reference register register register register register register register register register register register register register register power-on reset refcomp refin/outv cc gnd dac a ref dac h v outh dac g v outg dac f v outf dac e v oute porselsda scl reflo v outa dac b v outb dac c v outc dac d v outd ca2 ldac ca0 ca1 2-wire interface 32-bit shift register 2657 bd inl vs code (ltc2657-16) code 128 inl (lsb) 0 1 2 65535 2657 ta01 C1C2 C4 16384 32768 49152 C3 43 dac a dac b dac c dac d dac e dac f dac g dac h downloaded from: http:///
ltc2657 2 2657f pin configuration absolute maximum ratings supply voltage (v cc ) ................................... C0.3v to 6v scl, sda, ldac , reflo .............................. C0.3v to 6v v outa to v outh ................. C0.3v to min(v cc + 0.3v, 6v) refin/out, refcomp ...... C0.3v to min(v cc + 0.3v, 6v) porsel, ca0, ca1, ca2 ... C0.3v to min(v cc + 0.3v, 6v) (notes 1, 2) fe package 20-lead plastic tssop 12 3 4 5 6 7 8 9 10 top view 2019 18 17 16 15 14 13 12 11 reflo v outa v outb refcomp v outc v outd refin/out ldac ca2scl gndv cc v outh v outg v outf v oute porselca0 ca1 sda 21 t jmax = 150c, ja = 38c/w, jc = 10c/w exposed pad (pin 21) is gnd, must be soldered to pcb 20 19 18 17 7 8 top view 21 ufd package 20-lead (4mm s 5mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 v outb refcomp v outc v outd refin/out ldac v outh v outg v outf v oute porselca0 v outa reflognd v cc ca2scl sda ca1 t jmax = 150c, ja = 43c/w exposed pad (pin 21) is gnd, must be soldered to pcb operating temperature range ltc2657c ................................................ 0c to 70c ltc2657i..............................................C40c to 85c maximum junction temperature........................... 150c storage temperature range .......................C65 to 150c lead temperature (soldering fe-package, 10 sec) .. 300c downloaded from: http:///
ltc2657 3 2657f product selector guide ltc2657 b c ufd -l 16 #tr pbf lead free designator tape and reel tr = tape and reel resolution 16 = 16-bit 12 = 12-bit full-scale voltage, internal reference mode l = 2.5v h = 4.096v package type ufd = 20-lead (4mm 5mm) plastic qfn fe = 20-lead thermally enhanced tssop temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) electrical grade (optional) b = 4lsb inl (max) product part number consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc2657 4 2657f order information lead free finish tape and reel part marking* package description temperature range maximum inl ltc2657bcfe-l16#pbf ltc2657bcfe-l16#trpbf ltc2657fe-l16 20-lead thermally enhanced tssop 0c to 70c 4 ltc2657bife-l16#pbf ltc2657bife-l16#trpbf ltc2657fe-l16 20-lead thermally enhanced tssop C40c to 85c 4 ltc2657bcufd-l16#pbf ltc2657bcufd-l16#trpbf 57l16 20-lead (4mm 5mm) plastic qfn 0c to 70c 4 ltc2657biufd-l16#pbf ltc2657biufd-l16#trpbf 57l16 20-lead (4mm 5mm) plastic qfn C 40c to 85c 4 ltc2657bcfe-h16#pbf ltc2657bcfe-h16#trpbf ltc2657fe-h16 20-lead thermally enhanced tssop 0c to 70c 4 ltc2657bife-h16#pbf ltc2657bife-h16#trpbf ltc2657fe-h16 20-lead thermally enhanced tssop C40c to 85c 4 ltc2657bcufd-h16#pbf ltc2657bcufd-h16#trpbf 57h16 20-lead (4mm 5mm) plastic qfn 0c to 70c 4 ltc2657biufd-h16#pbf ltc2657biufd-h16#trpbf 57h16 20-lead (4mm 5mm) plastic qfn C 40c to 85c 4 ltc2657cfe-l12#pbf ltc2657cfe-l12#trpbf ltc2657fe-l12 20-lead thermally enhanced tssop 0c to 70c 1 ltc2657ife-l12#pbf ltc2657ife-l12#trpbf ltc2657fe-l12 20-lead thermally enhanced tssop C40c to 85c 1 ltc2657cufd-l12#pbf ltc2657cufd-l12#trpbf 57l12 20-lead (4mm 5mm) plastic qfn 0c to 70c 1 ltc2657iufd-l12#pbf ltc2657iufd-l12#trpbf 57l12 20-lead (4mm 5mm) plastic qfn C 40c to 85c 1 ltc2657cfe-h12#pbf ltc2657cfe-h12#trpbf ltc2657fe-h12 20-lead thermally enhanced tssop 0c to 70c 1 ltc2657ife-h12#pbf ltc2657ife-h12#trpbf ltc2657fe-h12 20-lead thermally enhanced tssop C40c to 85c 1 ltc2657cufd-h12#pbf ltc2657cufd-h12#trpbf 57h12 20-lead (4mm 5mm) plastic qfn 0c to 70c 1 ltc2657iufd-h12#pbf ltc2657iufd-h12#trpbf 57h12 20-lead (4mm 5mm) plastic qfn C 40c to 85c 1 consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container.c onsult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2657b-l16/ltc2657-l12 (internal reference = 1.25v) symbol param eter conditions ltc2657-12 ltc2657b-16 units min typ max min typ max dc performance resolution l 12 16 bits monotonicity (note 3) l 12 16 bits dnl differential nonlinearity (note 3) l 0.1 0.5 0.3 1 lsb inl integral nonlinearity (note 3) v cc = 5.5v, v ref = 2.5v l 0.5 1 2 4 lsb load regulation v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.125 0.6 2 lsb/ma v cc = 3v 10%, internal reference, mid-scale, C7.5ma i out 7.5ma l 0.06 0.25 1 4 lsb/ma zse zero-scale error l 13 13 m v v os offset error (note 4) v ref = 1.25v l 1 2 1 2 mv v os temperature coef? cient 2 2 v/c ge gain error l 0.02 0.1 0.02 0.1 %fsr gain temperature coef? cient 1 1 ppm/c downloaded from: http:///
ltc2657 5 2657f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2657b-l16/ltc2657-l12 (internal reference = 1.25v) symbol parameter conditions min typ max units v out dac output span internal reference external reference = v extref 0 to 2.5 0 to 2 ? v extref vv psr power supply rejection v cc 10% C80 db r out dc output impedance v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.15 v cc = 3v 10%, internal reference, mid-scale, C7.5ma i out 7.5ma l 0.04 0.15 dc crosstalk (note 5) due to full-scale output change due to load current changedue to powering down (per channel) 1.5 21 v v/ma v i sc short-circuit output current (note 6) v cc = 5.5v, v extref = 2.8v code: zero-scale, forcing output to v cc code: full-scale, forcing output to gnd ll 2020 6565 mama v cc = 2.7v, v extref = 1.4v code: zero-scale, forcing output to v cc code: full-scale, forcing output to gnd ll 1010 4040 mama reference reference output voltage 1.248 1.25 1.252 v reference temperature coef? cient (note 7) c-grade only 2 10 ppm/c reference line regulation v cc 10% C80 db reference short-circuit current v cc = 5.5v, forcing refin/out to gnd l 5m a refcomp pin short-circuit current v cc = 5.5v, forcing refcomp to gnd l 200 a reference load regulation v cc = 3v 10% or 5v 10%, i out = 100a sourcing 40 mv/ma reference output voltage noise density c refcomp = c refin/out = 0.1f at f = 1khz 30 nv/ hz reference input range external reference mode (note 14) l 0.5 v cc /2 v reference input current l 0.001 1 a reference input capacitance (note 9) 40 pf power supplyv cc positive supply voltage for speci? ed performance l 2.7 5.5 v i cc supply current (note 8) v cc = 5v, internal reference on v cc = 5v, internal reference off v cc = 3v, internal reference on v cc = 3v, internal reference off ll l l 3.12.7 3 2.6 4.25 3.73.8 3.2 mama ma ma i sd supply current in shutdown mode (note 8) v cc = 5v l 3 a digital i/ov il low level input voltage (sda and scl) l 0.3v cc v v ih high level input voltage (sda and scl) l 0.7v cc v v il( ldac ) low level input voltage ( ldac )v cc = 4.5v to 5.5v l 0.8 v v cc = 2.7v to 4.5v l 0.6 v v ih( ldac ) high level input voltage ( ldac )v cc = 3.6v to 5.5v l 2.4 v v cc = 2.7v to 3.6v l 2 v downloaded from: http:///
ltc2657 6 2657f symbol parameter conditions min typ max units v il(ca) low level input voltage (ca0 and ca2) see test circuit 1 l 0.15v cc v v ih(ca) high level input voltage (ca0 and ca2) see test circuit 1 l 0.85v cc v r inh resistance from ca n (n = 0,1, 2) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from ca n (n = 0,1, 2) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n (n = 0,1, 2) to v cc or gnd to set ca n =float see test circuit 2 l 2m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 13) l 20+0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 05 0 n s i in input leakage 0.1v cc v in 0.9vcc l 1 a c in i/o pin capacitance (note 9) l 10 pf c b capacitance load for each bus line l 400 pf c ca n external capacitive load on address pins ca0, ca1 and ca2 l 10 pf electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2657b-l16/ltc2657-l12 (internal reference = 1.25v) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2657b-h16/ltc2657-h12 (internal reference = 2.048v) symbol param eter conditions ltc2657-12 ltc2657b-16 units min typ max min typ max dc performance resolution l 12 16 bits monotonicity (note 3) l 12 16 bits dnl differential nonlinearity (note 3) l 0.1 0.5 0.3 1 lsb inl integral nonlinearity (note 3) v cc = 5.5v, v ref = 2.5v l 0.5 1 2 4 lsb load regulation v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.125 0.6 2 lsb/ma zse zero-scale error l 13 13 m v v os offset error (note 4) v ref = 2.048v l 1 2 1 2 mv v os temperature coef? cient 2 2 v/c ge gain error l 0.02 0.1 0.02 0.1 %fsr gain temperature coef? cient 1 1 ppm/c downloaded from: http:///
ltc2657 7 2657f symbol parameter conditions min typ max units v out dac output span internal reference external reference = v extref 0 to 4.096 0 to 2 ? v extref vv psr power supply rejection v cc 10% C80 db r out dc output impedance v cc = 5v 10%, internal reference, mid- scale,C15ma i out 15ma l 0.04 0.15 dc crosstalk due to full-scale output change due to load current changedue to powering down (per channel) 1.5 21 v v/ma v i sc short-circuit output current (note 4) v cc = 5.5v, v extref = 2.8v code: zero-scale, forcing output to v cc code: full-scale, forcing output to gnd ll 2020 6565 mama reference reference output voltage 2.044 2.048 2.052 v reference temperature coef? cient (note 7) c-grade only 2 10 ppm/c reference line regulation v cc 10% C80 db reference short-circuit current v cc = 5.5v, forcing refin/out to gnd l 5m a refcomp pin short-circuit current v cc = 5.5v, forcing refcomp to gnd l 200 a reference load regulation v cc = 3v 10% or 5v 10%, i out = 100a sourcing 40 mv/ma reference output voltage noise density c refcomp = c refin/out = 0.1f at f = 1khz 35 nv/ hz reference input range external reference mode (note 14) l 0.5 v cc /2 v reference input current l 0.001 1 a reference input capacitance (note 9) l 40 pf power supplyv cc positive supply voltage for speci? ed performance l 4.5 5.5 v i cc supply current (note 8) v cc = 5v, internal reference on v cc = 5v, internal reference off ll 3.3 3 4.25 3.7 mama i sd supply current in shutdown mode (note 8) v cc = 5v l 3 a digital i/ov il low level input voltage (sda and scl) l 0.3v cc v v ih high level input voltage (sda and scl) l 0.7v cc v v il( ldac ) low level input voltage ( ldac ) v cc = 4.5v to 5.5v l 0.8v v v ih( ldac ) high level input voltage ( ldac ) v cc = 4.5v to 5.5v l 2.4 v v il(ca) low level input voltage (ca0 to ca2) see test circuit 1 l 0.15v cc v v ih(ca) high level input voltage (ca0 to ca2) see test circuit 1 l 0.85v cc v r inh resistance from ca n (n = 0,1, 2) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from ca n (n = 0,1, 2) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n (n = 0,1, 2) to v cc or gnd to set ca n = float see test circuit 2 l 2m v ol low level ouput voltage sink current = 3ma l 0 0.4 v electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2657b-h16/ltc2657-h12 (internal reference = 2.048v) downloaded from: http:///
ltc2657 8 2657f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2657b-h16/ltc2657-h12 (internal reference = 2.048v) symbol parameter conditions min typ max units t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 13) l 20+0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 05 0 n s i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 9) l 10 pf c b capacitance load for each bus line l 400 pf c ca n external capacitive load on address pins ca0, ca1 and ca2 l 10 pf symbol parameter conditions min typ max units ac performancet s settling time (note 10) 0.024% (1lsb at 12 bits) 0.0015% (1lsb at 16 bits) 3.99.1 ss settling time for 1lsb step 0.024% (1lsb at 12 bits) 0.0015% (1lsb at 16 bits) 2.44.5 ss voltage output slew rate 1.8 v/s capacitive load driving 1000 pf glitch impulse (note 11) at mid-scale transition, l-option 4 nv?s at mid-scale transition, h-option 7 nv?s dac-to-dac crosstalk (note 12) c refcomp = c refin/out = 0.22f 0.8 nv?s multiplying bandwidth 150 khz e n output voltage noise density at f = 1khz at f = 10khz 8580 nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, internal reference (l-options) 0.1hz to 10hz, internal reference (h-options)0.1hz to 200khz, internal reference (l-options) 0.1hz to 200khz, internal reference (h-options) 8 12 600650 v p-p v p-p v p-p v p-p the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2657b-h16/ltc2657-h12/ ltc2657b-l16/ltc2657-l12 downloaded from: http:///
ltc2657 9 2657f timing characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd. note 3: linearity and monotonicity are de? ned from code kl to code 2 n C 1, where n is the resolution and kl is the lower end code for which no output limiting occurs. for v ref = 2.5v and n = 16, kl = 128 and linearity is de? ned from code 128 to code 65535. for v ref = 2.5v and n = 12, kl = 8 and linearity is de? ned from code 8 to code 4,095. note 4: inferred from measurement at code 128 (ltc2657-16) or code 8 (ltc2657-12). note 5: dc crosstalk is measured with v cc = 5v and using internal reference with the measured dac at mid-scale.note 6: this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. symbol parameter conditions min typ max units v cc = 2.7v to 5.5v f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su(sta) set-up time for a repeated start program l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time of both sda and scl signals l 20+0.1c b 300 ns t f fall time of both sda and scl signals l 20+0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s t 1 falling edge of the 9th clock of the 3rd input byte to ldac high or low transition l 400 ns t 2 ldac low pulse width l 20 ns the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ltc2657b-l16/ltc2657-l12/ltc2657b-h16/ltc2657-h12 (see figure 1). note 7: temperature coef? cient is calculated by dividing the maximum change in output voltage by the speci? ed temperature range. note 8: digital inputs at 0v or v cc . note 9: guaranteed by design and not production tested. note 10: internal reference mode. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 200pf to gnd.note 11: v cc = 5v (h-options) or v cc = 3v (l-options), internal reference mode. dac is stepped 1lsb between half-scale and half-scale C1. load is 2k in parallel with 200pf to gnd. note 12: dac-to-dac crosstalk is the glitch that appears at the output of one dac due to a full-scale change at the output of another dac. it is measured with v cc = 5v, using internal reference, with the measured dac at mid-scale.note 13: c b = capacitance of one bus line in pf. note 14: gain error speci? cation may be degraded for reference input voltages less than 1v. see gain error vs reference input curve in the typical performance characteristics section. downloaded from: http:///
ltc2657 10 2657f typical performance characteristics temperature (c) C50 v refin/out (v) 1.2511.250 1.249 1.248 1.247 1.252 C10 30 50 130 2657 g05 C30 10 70 90 110 1.253 v cc = 3v dnl vs temperature refin/out output voltage vs temperature settling to 1lsb rising settling to 1lsb falling integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature ltc2657-l16, t a = 25c unless otherwise noted. code 128 C4 inl (lsb) 32 1 0 C1C2 C3 4 16384 65535 32768 2657 g01 49152 v cc = 3v code 128 C1 dnl (lsb) 0.5 0 C0.5 1 16384 65535 32768 2657 g02 49152 v cc = 3v temperature (c) C50 C4 inl (lsb) 32 1 0 C1C2 C3 4 C30 70 90 110 130 C10 10 30 2657 g03 50 v cc = 3v inl (pos) inl (neg) temperature (c) C50 C1 dnl (lsb) 0.5 0 C0.5 1 C30 70 90 110 130 C10 10 30 3586 g35 50 dnl (pos) v cc = 3v dnl (neg) 2s/div scl 3v/div v out 150v/div 2657 g07 1/4 scale to 3/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 200pf average of 2048 events 9th clock of 3rd data byte 9s 2s/div scl 3v/div v out 100v/div 2657 g08 8.6s 9th clock of 3rd data byte 3/4 scale to 1/4 scale stepv cc = 3v, v fs = 2.5v r l = 2k, c l = 200pf average of 2048 events downloaded from: http:///
ltc2657 11 2657f temperature (c) C50 v refin/out (v) 2.0502.048 2.046 2.044 2.042 2.052 C10 30 50 130 2657 g14 C30 10 70 90 110 2.054 v cc = 5v dnl vs temperature refin/out output voltage vs temperature settling to 1lsb rising settling to 1lsb falling integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature typical performance characteristics ltc2657-h16, t a = 25c unless otherwise noted. code 128 C4 inl (lsb) 32 1 0 C1C2 C3 4 65535 16384 32768 49152 2657 g10 v cc = 5v code 128 C1 dnl (lsb) 0.5 0 C0.5 1 65535 16384 32768 2657 g011 49152 v cc = 5v temperature (c) C50 C4 inl (lsb) 32 1 0 C1C2 C3 4 C30 70 90 110 130 C10 10 30 3586 g35 50 v cc = 5v inl (pos) inl (neg) temperature (c) C50 C1 dnl (lsb) 0.5 0 C0.5 1 C30 70 90 110 130 C10 10 30 2657 g13 50 v cc = 5v dnl (pos) dnl (neg) 2s/div 2657 g16 v out 250v/div scl 5v/div 9th clock of 3rd data byte 9.7s 1/4 scale to 3/4scale step v cc = 5v, v fs = 4.096v r l = 2k, c l = 200pf average of 2048 events 2s/div 2657 g17 v out 250v/div scl 5v/div 9.2s 9th clock of 3rd data byte 3/4 scale to 1/4 scale step v cc = 5v, v fs = 4.096v r l = 2k, c l = 200pf average of 2048 events downloaded from: http:///
ltc2657 12 2657f i out (ma) C50 v out (mv) 2 6 10 30 2657 g22 C4 0 4 8 C2C6 C8 C10 C30 C40 C10 C20 10 20 40 0 50 v cc = 5v (ltc2657-h) v cc = 3v (ltc2657-l) internal ref.code = mid-scale i out (ma) C50 v out (v) 0 0.10 0.20 30 2657 g23 C0.10 C0.05 0.05 0.15 C0.15C0.20 C30 C40 C10 C20 10 20 40 0 50 v cc = 5v (ltc2657-h) v cc = 3v (ltc2657-l) internal ref.code = mid-scale i out (ma) 0 v out (v) 3.0 4.0 5.0 8 2657 g24 2.01.0 2.5 3.5 4.51.5 0.5 0 2 1 4 3 67 9 5 10 5v ourcing 5v inking 3v ourcing (ltc2657-l) 3v inking (ltc2657-l) load regulation current limiting headroom at rails vs output current offset error vs temperature zero-scale error vs temperature gain eror vs temperature integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb typical performance characteristics ltc2657-12, t a = 25c unless otherwise noted. code 8 C1 inl(lsb) 0.5 0 C0.5 1 4095 1024 2048 2657 g19 3072 v cc = 5v v ref = 2.048v code 8 C1 dnl(lsb) 0.5 0 C0.5 1 4095 1024 2048 2657 g20 3072 v cc = 5v v ref = 2.048v 2s/div 2657 g21 v out 500v/div scl 3v/div 3.5s 9th clock of 3rd data byte 3/4 scale to 1/4 scale stepv cc = 3v, v fs = 2.5v r l = 2k, c l = 200pf average of 2048 events temperature (c) C50 C1 offset error (mv) 0.750.25 0.5 0 C0.25 C0.5 C0.75 1 C30 70 90 110 130 C10 10 30 2657 g25 50 temperature (c) C50 0 zero-scale error (mv) 2 2.51.5 1 0.5 3 C30 70 90 110 130 C10 10 30 2657 g26 50 temperature (c) C50 C64 gain error (lsb) 4832 16 0 C16C32 C48 64 C30 70 90 110 130 C10 10 30 2657 g27 50 ltc2657 downloaded from: http:///
ltc2657 13 2657f supply current vs logic voltage supply current vs temperature i cc shutdown vs temperature multiplying bandwidth large signal response mid-scale glitch impulse offset error vs reference input gain error vs reference input i cc shutdown vs v cc typical performance characteristics ltc2657, t a = 25c unless otherwise noted. reference voltage (v) 0.5 C2 offset error (mv) 1.5 1 0.5 0 C 0.5 C1 C1.5 2 2.5 1 1.5 2657 g28 2 v cc = 5.5v gain error of 8 channels reference voltage (v) 0.5 C64 gain error (lsb) 4832 16 0 C16C32 C48 64 2.5 1 1.5 2657 g29 2 v cc = 5.5v gain error of 8 channels v cc (v) 2.5 0 i cc (na) 400350 300 250 200 150 100 50 450 3.0 5.0 5.5 3.5 4.0 4.5 2657 g30 logic voltage (v) 0 2.0 i cc (ma) 3.63.2 2.8 2.4 4.0 15 234 2657 g31 v cc = 5v (ltc2657-h) v cc = 3v (ltc2657-l) sweep scl, sda between ov and v cc temperature (c) C50 2.0 supply current (ma) 3.53.0 2.5 4.0 C30 70 90 110 130 C10 10 30 2657 g32 50 ltc2657-h v cc = 5v, code = mid-scale internal reference ltc2657-l v cc = 3v, code = mid-scale internal reference temperature (c) C50 0 i cc shutdown (a) 21 3 C30 70 90 110 130 C10 10 30 2657 g33 50 ltc2657-h v cc = 5v ltc2657-l v cc = 3v frequency (hz) 1k C12 amplitude (db) 64 2 0 C2 C4C6 C8 C10 8 1m 10k 2657 g34 100k v cc = 5v v ref(dc) = 2v v ref(ac) = 0.2v pp code = full-scale 2s/div 2657 g35 v out 0.5v/div v cc = 5v v ref = 2.048v zero scale to full scale 2s/div 2657 g36 scl 5v/div v out 5mv/div ltc2657-h16, v cc = 5v 7nv-s typ ltc2657-l16, v cc = 3v 4nv-s typ 9th clock of 3rd data byte downloaded from: http:///
ltc2657 14 2657f 2657 g38 200s/div v cc 2v/div v out 10mv/div zero-scale 2657 g39 250s/div v cc 2v/div v out 1v/div ltc2657-h frequency (hz) 11 0 noise voltage (nv/ hz ) 200 400 600 800 100 1k 10k 100k 1m 2657 g40 0 1000 1200 ltc2657-h ltc2657-l v cc = 5v code = mid-scaleinternal ref c refcomp = c refout = 0.1f 2v/div 2657 g42 1 sec/div v refout = 1.25v c refcomp = c refout = 0.1f noise voltage density vs frequency dac output 0.1hz to 10hz voltage noise reference output 0.1hz to 10hz voltage noise dac to dac crosstalk (dynamic) power on reset to zero-scale power on reset to mid-scale 5v/div 2657 g41 1 sec/div v cc = 5v, v fs = 2.5v code = mid-scaleinternal ref c refcomp = c refout = 0.1f typical performance characteristics ltc2657 2s/div 2657 g37 v out 0.5mv/div one dac switch fs-0 2v/div ltc2657-h16, v cc = 5v, 0.8nv ? s typ c refcomp = c refout = 0.22f downloaded from: http:///
ltc2657 15 2657f pin functions v outa to v outh (pins 1, 3, 4, 13, 14, 15, 16, 20/pins 2, 3, 5, 6, 15, 16, 17, 18): dac analog voltage outputs. the output range is 0v to 2 times the voltage at the refin/out pin. refcomp (pin 2/pin 4): internal ref erence compensation pin. for low noise and reference stability, tie 0.1f cap to gnd. connect to gnd to use an external reference at start-up. command 0111b must still be issued to turn off internal reference. refin/out (pin 5/pin 7): this pin acts as the internal reference output in internal reference mode and acts as the reference input pin in external reference mode. when acting as an output the nominal voltage at this pin is 1.25v for-l options and 2.048v for-h options. for low noise and reference stability tie a capacitor to gnd. capacitor value must be <= c refcomp . in external reference mode, the allowable reference input voltage range is 0.5v to v cc /2 . ldac (pin 6/pin 8): asynchronous dac update pin. a falling edge on this input after four bytes have been written into the part immediately updates the dac register with the contents of the input register. a low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the dac output. software power- down is disabled when ldac is low. ca2 (pin 9/pin 7): chip address bit 2. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (see table 2). scl (pin 8/pin 10): serial clock input pin. data is shifted into the sda pin at the rising edges of the clock. this high impedance pin requires a pull-up resistor or current source to v cc . sda (pin 9/pin 11 ): serial data bidi rectional pin. data is shifted into the sda pin and acknowledged by the sda pin. this is a high impedance pin while data is shifted in. it is an open-drain n-channel output during acknowledgement. this pin requires a pull-up resistor or current source to v cc . ca1 (pin 10/pin 12): chip address bit 1. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (see table 2) ca0 (pin 11/pin 13): chip address bit 0. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (see table 2). porsel (pin 12/pin 14): power-on-reset select pin. if tied to gnd, the part resets to zero-scale at power up. if tied to v cc , the part resets to mid-scale at power up. v cc (pin 17/pin 19): supply voltage input. for Cl options, 2.7v v cc 5.5v, and for Ch options, 4.5v v cc 5.5v. bypass to ground with a 0.1f capacitor placed as close to pin as possible.gnd (pin 18/pin 20): ground. reflo (pin 19/pin 1): reference low pin. the voltage at this pin sets the zero-scale voltage of all dacs. this pin should be tied to gnd. exposed pad (pin 21/pin 21): ground. must be soldered to pcb ground. (qfn/tssop) downloaded from: http:///
ltc2657 16 2657f block diagram test circuit register register internal reference register register register register register register register register register register register register register register power-on reset refcomp refin/outv cc gnd dac a ref dac h v outh dac g v outg dac f v outf dac e v oute porselsda scl reflo v outa dac b v outb dac c v outc dac d v outd ca2 ldac ca0 ca1 2-wire interface 32-bit shift register 2657 bd 100 7 r inh /r inl /r inf v ih(ca n ) /v il(ca n ) ca n gnd 2606 tc v dd test circuit 2 test circuit 1 ca n downloaded from: http:///
ltc2657 17 2657f timing diagram sda t f s t r t low t hd(sta) all voltage levels refer to v ih(min) and v il(max) levels t hd(dat) t su(dat) t su(sta) t hd(sta) t su(sto) t sp t buf t r t f t high scl s r p s 2657 f01 9th clock of 3rd data byte t 1 scl ldac 2657 f01b figure 1 downloaded from: http:///
ltc2657 18 2657f operation the ltc2657 is a family of octal voltage output dacs in 20-lead 4mm 5mm qfn and in 20-lead thermally enhanced tssop packages. each dac can operate rail-to-rail in external reference mode, or with its full-scale voltage set by an integrated reference. four combinations of accuracy (16- and 12-bit), and full-scale voltage (2.5v or 4.096v) are available. the ltc2657 is controlled using a 2-wire i 2 c compatible interface. power-on reset the ltc2657-l/-h clear the output to zero-scale if the porsel pin is tied to gnd when power is ? rst applied, making system initialization consistent and repeatable. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2657 contains circuitry to reduce the power-on glitch. the analog outputs typically rise less than 10mv above zero-scale during power on if the power supply is ramped to 5v in 1ms or more. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics section. alternatively, if porsel is tied to v cc , the ltc2657-l/-h set the output to mid-scale when power is ? rst applied. power supply sequencing and start-up for the ltc2657 family of parts, the internal reference is powered-up at start-up by default. if an external reference is to be used, the refcomp pin (pin 4 Ctssop, pin 2 -qfn ) must be hardwired to gnd. this con? guration allows the use of an external reference at start-up and converts the refin/out pin to an input. however, the internal reference will still be on and draw supply current. in order to use an external reference, command 0111b should be used to turn the internal reference off.(see table1.) the voltage at refin/out (pin 7 Ctssop, pin 5 -qfn) should be kept within the range C0.3v refin/out v cc + 0.3v (see absolute maximum ratings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 19 Ctssop, pin 17 -qfn ) is in transition. transfer function the digital-to-analog transfer function is: v k v reflo refl out ideal n ref () ? = ? ? ? ? ? ? ? ?? ?? + 2 2o o where k is the decimal equivalent of the binary dac input code, n is the resolution, and v ref is the voltage at the refin/out pin. the resulting dac output span is 0v to 2 ? v ref , as it is necessary to tie reflo to gnd. v ref is nominally 1.25v for ltc2657-l and 2.048v for ltc2657-h, in internal reference mode. table 1. command and address codes command* c3 c2 c1 c0 0 0 0 0 write to input register n 0 0 0 1 update (power up) dac register n 0 0 1 0 write to input register n, update (power up) all 0 0 1 1 write to and update (power up) n 0 1 0 0 power down n 0 1 0 1 power down chip (all dacs and reference) 0 1 1 0 select internal reference (power-up reference) 0 1 1 1 select external reference (power-down reference) 1 1 1 1 no operation address (n)* a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 0 1 0 0 dac e 0 1 0 1 dac f 0 1 1 0 dac g 0 1 1 1 dac h 1 1 1 1 all dacs *command and address codes not shown are reserved and should not be used. serial interface the ltc2657 communicates with a host using the stan- dard 2-wire i 2 c interface. the timing diagrams (figures 1 and 2) show the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the value of downloaded from: http:///
ltc2657 19 2657f operation these pull-up resistors is dependent on the power supply and can be obtained from the i 2 c speci? cations. for an i 2 c bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pf. the ltc2657 is a receive-only (slave) device. the master can write to the ltc2657. the ltc2657 does not respond to a read command from the master. the start (s) and stop (p) conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communication to a slave device by transmitting a start condition (see figure 1). a start condition is generated by transitioning sda from high to low while scl is high. when the master has ? nished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. acknowledgethe acknowledge signal is used for handshaking between the master and the slave. an acknowledge (active low) generated by the slave lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock pulse. the slave-receiver must pull down the sda bus line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. the ltc2657 responds to a write by a master in this manner. the ltc2657 does not acknowledge a read (retains sda high during the period of the acknowledge clock pulse). chip address the state of ca0, ca1 and ca2 decides the slave address of the part. the pins ca0, ca1 and ca2 can be each set to any one of three states: v cc , gnd or ? oat. this results in 27 selectable addresses for the part. the slave address assignments are shown in table 2. table 2. slave address map ca2 ca1 ca0 a6 a5 a4 a3 a2 a1 a0 gnd gnd gnd 0 0 1 0 0 0 0 gnd gnd float 0 0 1 0 0 0 1 gnd gnd v cc 0010010 gnd float gnd 0 0 1 0 0 1 1 gnd float float 0 1 0 0 0 0 0 gnd float v cc 0100001 gnd v cc g n d0100010 gnd v cc float 0 1 0 0 0 1 1 gnd v cc v cc 0110000 float gnd gnd 0 1 1 0 0 0 1 float gnd float 0 1 1 0 0 1 0 float gnd v cc 0110011 float float gnd 1 0 0 0 0 0 0 float float float 1 0 0 0 0 0 1 float float v cc 1000010 float v cc g n d1000011 float v cc float 1 0 1 0 0 0 0 float v cc v cc 1010001 v cc gnd gnd 1 0 1 0 0 1 0 v cc gnd float 1 0 1 0 0 1 1 v cc gnd v cc 1100000 v cc float gnd 1 1 0 0 0 0 1 v cc float float 1 1 0 0 0 1 0 v cc float v cc 1100011 v cc v cc g n d1110000 v cc v cc float 1 1 1 0 0 0 1 v cc v cc v cc 1110010 global address 1 1 1 0 0 1 1 in addition to the address selected by the address pins, the parts also respond to a global address. this address allows a common write to all ltc2657 parts to be accomplished with one 3-byte write transaction on the i 2 c bus. the global address is a 7-bit on-chip hardwired address and is not selectable by ca0, ca1 and ca2. the addresses corresponding to the states of ca0, ca1 and ca2 and the global address are shown in table 2. the maximum capacitive load allowed on the address pins (ca0, ca1 and ca2) is 10pf, as these pins are driven during address detection to determine if they are ? oating. downloaded from: http:///
ltc2657 20 2657f operation write word protocol the master initiates communication with the ltc2657 with a start condition and a 7-bit slave address followed by the write bit (w) = 0. the ltc2657 acknowledges by pulling the sda pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by ca0, ca1 and ca2) or the global address. the master then transmits three bytes of write data. the ltc2657 acknowledges each byte of data by pulling the sda line low at the 9th clock of each data byte transmission. after receiving three complete bytes of data, the ltc2657 executes the command speci? ed in the 24-bit input word. if more than three data bytes are transmitted after a valid 7-bit slave address, the ltc2657 does not acknowledge the extra bytes of data (sda is high during the 9th clock). the ? rst byte of the input word consists of the 4-bit command followed by 4-bit address. the next two bytes consist of the 16-bit data word. the 16-bit data word consists of the 16- or 12-bit input code, msb to lsb, followed by 0 or 4 dont care bits (ltc2657- 16 and ltc2657-12, respectively). a typical ltc2657 write transaction is shown in figure 2. the command (c3-c0) and address (a3-a0) assignments are shown in table 1. the ? rst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register. in an update operation, the data word is copied from the input register to the dac register and converted to an analog voltage at the dac output. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram. power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight outputs are needed. when in power-down, the buffer ampli? ers, bias circuits and integrated reference circuits are disabled, and draw essentially zero current. the dac outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 80k resistors. input- and dac-register contents are not disturbed during power-down. any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate dac address, (n). the integrated reference is automatically powered down when external reference mode is selected using command 0111b. in addition, all the dac channels and the integrated reference together can be put into power-down mode using power-down chip command 0101b. for all power- down commands the 16-bit data word is ignored, but still required in order to complete a full communication cycle. normal operation resumes by executing any command which includes a dac update, in software as shown in table 1 or using the asynchronous ldac pin. the selected dac is powered up as its voltage output is updated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if less than eight dacs are in a powered-down state prior to the update command, the power-up delay time is 12s. if on the other hand, all eight dacs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual dac ampli? ers and reference inputs. in this case, the power up delay time is 14s. the power up of the integrated reference depends on the command that powered it down. if the reference is powered down using the select external reference command (0111b), then it can only be powered back up by sending select internal reference command (0110b). however if the reference was powered down by sending power down chip command (0101b), then in addition to select internal reference command (0110b), any command that powers up the dacs will also power up the integrated reference. reference modes for applications where an accurate external reference is not available, the ltc2657 has a user-selectable, integrated reference. the ltc2657-l has a 1.25v reference that provides a full-scale output of 2.5v. the ltc2657-h has a 2.048v reference that provides a full-scale output of 4.096v. both references exhibit a typical temperature drift of 2ppm/c. internal reference mode can be selected by using command 0110b, and is the power-on default. a buffer is needed if the internal reference is required to drive external circuitry. for reference stability and low noise, it is recommended that a 0.1f capacitor be tied between refcomp and gnd. in this con? guration, the downloaded from: http:///
ltc2657 21 2657f internal reference can drive up to 0.1f capacitive load without any stability problems. in order to ensure stable operation, the capacitive load on the refin/out pin should not exceed the capacitive load on the refcomp pin. the dac can also operate in external reference mode using command 0111b. in this mode, the refin/out pin acts as an input that sets the dacs reference voltage. the input is high impedance and does not load the external reference source. the acceptable voltage range at this pin is 0.5v refin/out v cc /2. the resulting full-scale output voltage is 2 ? v refin/out . for using external reference at start-up, see the power supply sequencing and start-up section.integrated reference buffers each of the eight dacs in ltc2657 has its own integrated high performance reference buffer. the buffers have very high input impedance and do not load the reference voltage source. these buffers shield the reference voltage from glitches caused by dac switching and thus minimize dac-to-dac dynamic crosstalk. see the curve dac- to-dac crosstalk (dynamic) in the typical performance characteristics section. voltage outputs each of the eight rail-to-rail ampli? ers contained in ltc2657 has guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the ampli? ers ability to maintain the rated voltage accuracy over a wide range of load conditions. the measured change in output voltage per milliampere of forced load current change is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the ampli? ers dc output impedance is 0.040 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 30 ? 1ma = 30mv. see the graph headroom at rails vs output current in the typical performance characteristics section. operation the ampli? ers are stable driving capacitive loads of up to 1000pf. board layout the excellent load regulation and dc crosstalk performance of these devices is achieved in part by keeping signal and power grounds separate. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the devices ground pin as possible. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin functions as a return path for power supply currents in the device and should be con-nected to analog ground. the reflo pin should be connected to system star ground. resistance from the reflo pin to system star ground should be as low as possible. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in figure 3b. similarly, limiting can occur in external refer- ence mode near full-scale when the refin/out pin is at v cc /2 . if v refin/out = v cc /2 and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 3c. no full-scale limiting can occur if v refin/out (v cc C fse)/2. offset and linearity are de? ned and tested over the region of the dac transfer function where no output limiting can occur. downloaded from: http:///
ltc2657 22 2657f operation ack ack 123456789123456789123456789123456789 2657 f02 ack start stop full-scale voltage zero-scale voltage sda sa6 sa5 sa4 sa3 sa2 sa1 sa0 scl v out c2 c3 c3 c2 c1 c0 a3 a2 a1 a0 c1 c0 a3 a2 a1 a0 ack command/address byte d15 d14 d13 d12 d11 d10 d9 d8 ms data byte d7 d6 d5 d4 d3 d2 d1 d0 ls data byte sa6 sa5 sa4 sa3 sa2 sa1 sa0 wr slave address figure 2. typical ltc2657 input waveform Cprogramming dac output for full-scale downloaded from: http:///
ltc2657 23 2657f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. operation 2657 f03 input code (b) output voltage negative offset 0v 32, 768 0 65, 535 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positivefse figure 3. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero-scale (c) effect of positive full-scale error for codes near full-scale fe20 (cb) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref recommended solder pad layout 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8910 11 12 14 13 6.40 C 6.60* (.252 C .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc package description fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation cb downloaded from: http:///
ltc2657 24 2657f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0909 printed in usa package description ufd package 20-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1711 rev b) 4.00 0.10 (2 sides) 5.00 0.10 (2 sides) note:1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (note 6) 0.75 0.05 0.200 ref 0.00 C 0.05 1.50 ref 0.40 0.10 19 20 12 bottom viewexposed pad 2.50 ref r = 0.115 typ pin 1 notchr = 0.20 or c = 0.35 0.25 0.05 0.50 bsc (ufd20) qfn 0506 rev b r = 0.05 typ 2.65 0.10 3.65 0.10 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.65 0.05 2.50 ref 4.10 0.055.50 0.05 1.50 ref 3.10 0.05 4.50 0.05 packageoutline 3.65 0.05 0.50 bsc 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package related parts part number description comments ltc1664 quad 10-bit v out dac in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1821 single 16-bit v out dac with 1lsb inl, dnl parallel interface, precision 16-bit settling in 2s for 10v step ltc2600/ltc2610/ ltc2620 octal 16-/14-/12-bit v out dacs in 16-lead narrow ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2601/ltc2611/ ltc2621 single 16-/14-/12-bit v out dacs in 10-lead dfn 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2602/ltc2612/ ltc2622 dual 16-/14-/12-bit v out dacs in 8-lead msop 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2604/ltc2614/ ltc2624 quad 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2605/ltc2615/ ltc2625 octal 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output ltc2606/ltc2616/ ltc2626 single 16-/14-/12-bit v out dacs with i 2 c interface 270a per dac, 2.7v to 5.5v supply range, rail-to-rail output ltc2609/ltc2619/ ltc2629 quad 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output with separate v ref pins for each dac ltc2637 octal i 2 c 12-/10-/8-bit v out dacs with 10ppm/c reference 125a per dac, 2.7v to 5.5v supply range, internal 1.25v or 2.048v reference, rail-to-rail output, i 2 c interface ltc2641/ltc2642 single 16-/14-/12-bit v out dacs with 1lsb inl, dnl 1lsb (max) inl, dnl, 3mm 3mm dfn and msop packages, 120a supply current, spi interface ltc2704 q uad 16-/14-/12-bit v out dacs with 2lsb inl, 1l sb dnl software programmable output ranges up to 10v, spi interface ltc2754 q uad 16-/14-/12-bit i out dacs with 1lsb inl, 1lsb dnl s oftware programmable output ranges up to 10v, spi interface ltc2656 octal 16-/12-bit v out dacs with 4 lsb inl, 1 lsb dnl 4mm 5mm qfn-20, tssop-20 packages, spi packages, internal 10ppm/c (max) reference downloaded from: http:///

▲Up To Search▲

Price & Availability of LTC2657BCUFD-H16PBF

	To Download LTC2657BCUFD-H16PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .